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71M6543F/71M6543G Data Sheet
Table 47: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15
SEGDIO
Pin #
0
45
1
44
2
43
3
42
4
41
5
39
6
38
7
37
8
36
9
35
10
34
11
33
12
32
13
31
14
30
15
29
Configuration:
0 = DIO, 1 = LCD
0
1 2 3 4 5 6
LCD_MAP[7:0] (I/O RAM 0x240B)
7
0
1 2 3 4 5 6
LCD_MAP[15:8] (I/O RAM 0x240A)
7
SEG Data Register
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
15
DIO Data Register
Direction Register:
0 = input, 1 = output
0
4
1 2
P0 ( SFR80 )
5 6
P0 ( SFR 0x80 )
3
7
0
4
1 2
P1 (SFR 0x90)
5 6
P1 ( SFR 0x90 )
3
7
0
4
1 2
P2 ( SFR 0xA0 )
5 6
P2 ( SFR 0xA0 )
3
7
0
4
1 2
P3 ( SFR 0xB0 )
5 6
P3 ( SFR 0xB0 )
3
7
Internal Resources
Configurable
(see Table 46 )
–
–
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 48 , and the configuration for pins
SEGDIO32 to SEGDIO45 is shown in Table 49 . The configuration for pins SEGDIO51 to SEGDIO55 is
shown in Table 50.
Table 48: Data/Direction Registers for SEGDIO16 to SEGDIO31
SEGDIO
Pin #
16
28
17
27
18
25
19
24
20
23
21
22
22
21
23
20
24
19
25
18
26
17
27
16
28
11
29
10
30
9
31
8
Configuration:
0 = DIO, 1 = LCD
0
1 2 3 4 5 6
LCD_MAP[23:16] (I/O RAM 0x2409)
7
0
1 2 3 4 5 6
LCD_MAP[31:24] (I/O RAM 0x2408)
7
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
16
16
16
17
17
17
18
18
18
19
19
19
20 21 22 23 24 25 26 27
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
20 21 22 23 24 25 26 27
LCD_SEGDIO16[0 ] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
20 21 22 23 24 25 26 27
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
28
28
28
29
29
29
30
30
30
31
31
31
Table 49: Data/Direction Registers for SEGDIO32 to SEGDIO45
SEGDIO
Pin #
32
7
33
6
34
5
35
4
36
3
37
2
38
1
39
100
40
99
41
98
42
97
43
96
44
95
45
94
Configuration:
0 = DIO, 1 = LCD
0
1
2 3 4 5
LCD_MAP[39:32]
(I/O RAM 0x2407)
6
7
0
1 2 3 4
LCD_MAP[45:40]
(I/O RAM 0x2406[5:0])
5
SEG Data Register
32
33
34
35 36 37 38 39 40 41 42
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
43
44
45
DIO Data Register
Direction Register:
0 = input, 1 = output
32
32
33
33
34
34
35 36 37 38 39 40 41
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
35 36 37 38 39 40 41
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
42
42
43
43
44
44
45
45
60
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